The present invention is concerned with a method of alignment, in particular, but not exclusively, with a method of angularly aligning semiconductor wafers during semiconductor lithographic processes associated with fabricating semiconductor devices.
Semiconductor wafers are conventionally angularly aligned in lithographic tools, for example in step-and-repeat cameras, by registering to one or more wafer flats formed in the wafers. When fabricating many types of semiconductor devices, for example logic devices such as dynamic memories, alignment of integrated circuit features, for example doped electrode regions and metal conductor tracks, to wafer crystal planes is not especially critical to device performance. However, high overlay accuracy of device layers is essential for achieving satisfactory device yield and operation.
In the case of micromachined devices, for example electro-optical devices such as solid-state lasers relying on the formation of mirror-like cleaved surfaces as functional components thereof, highly accurate angular alignment of device features to wafer crystal planes is critical. When this angular alignment is not accurately achieved, device dimensional tolerances become difficult to attain and cleaved surfaces can often include stepped features which are deleterious to device performance.
During conventional semiconductor wafer manufacture, groves aligned to wafer crystal planes are scribed on wafers and the wafers are then cleaved along the groves to form flats in the wafers. The wafers are then subjected to polishing operations because exposed abrupt cleaved surfaces can render the wafers vulnerable to shatter during subsequent processing steps, for example high temperature dopant activation processes, and can result in crystal dislocation defects propagating through the wafers. The polishing processes are effective at smoothing the abrupt cleaved surfaces.